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MoS Chandrasekhar Propels India’s Quest to Master RISC-V Innovation And Chip Design Excellence – News18


Union Minister of State for Skill Development & Entrepreneurship and Electronics & IT Rajeev Chandrasekhar (File pic/PTI)

The Digital India RISC-V (DIR-V) programme represents a huge opportunity for the startups in the design ecosystem in India to build the next generation of chips around RISC V processors and systems around DIR V devices, said Rajeev Chandrasekhar

Union Minister of State for Skill Development & Entrepreneurship and Electronics & IT Rajeev Chandrasekhar inaugurated the Nationwide Roadshow on Digital India RISC-V (DIR-V) programme, heralding a pivotal moment in India’s technological advancement. This collaborative effort between C-DAC, IEEE India Council, and the Ministry of Electronics & IT attracted global leaders in the RISC-V design realm.

Chandrasekhar highlighted the occasion, saying: “This is a significant milestone and tremendous progress that today we are able to demonstrate to the entire country the capabilities not just in broad chip design but in terms of high-performance chip design in RISC V domain.”

Underlining the government’s commitment, Chandrasekhar stressed, “The opportunities created in the last 7 years by PM Narendra Modi’s policies represent an unprecedented opportunity for success and growth…Our primary focus is to grow the RISC V and DIR V ecosystems.”

Expressing India’s ambition in the technological landscape, he stated: “It is certainly our ambition as a country and with hundreds and thousands of engineers amongst the audience that we will master and become if not the global leader but certainly amongst the world’s leading nations in propagating and navigating the capabilities and capacities to create innovation around the RISC V and DIR V family of chips and systems.”

Acknowledging the burgeoning startup ecosystem, Chandrasekhar emphasised that the DIR V ecosystem has seen many startups such as Ventana Micro Systems, Esperanto Technologies, InCore Semiconductors, Mindgrove Technologies, and Morphing Machines. According to him, the programme represents a huge opportunity for the startups in the design ecosystem in India to build the next generation of chips around RISC V processors and systems around DIR V devices.

Highlighting future application areas, he pointed out: “While RISC V has always represented open source and collaborative framework for innovation in semiconductor design and fabless design, today with the growing need for AI and machine learning DIR V will also be able to address high-performance computing and applications in the coming years.”

The nationwide roadshow aims to equip 1,500 participants with comprehensive insights into DIR-V VEGA processors and their ecosystem. Hands-on sessions, endorsed by global leaders like Prof Krste Asanovic and Calista Redmond, will empower participants from 15 academic institutions across India.



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